author = "Armelin, F{\'a}bio Batagin and Naviner, L{\'{\i}}rida Alves de 
                         Barros and d'Amore, Roberto",
          affiliation = "{Instituto Nacional de Pesquisas Espaciais (INPE)} and {Institut 
                         Polytechnique de Paris} and {Instituto Tecnol{\'o}gico de 
                         Aeron{\'a}utica (ITA)}",
                title = "Soft-error vulnerability estimation approach based on the set 
                         susceptibility of each gate",
              journal = "Electronics (Switzerland)",
                 year = "2019",
               volume = "8",
               number = "7",
                pages = "e749",
                month = "July",
             keywords = "Soft-Error, Single-Event Effect, Single-Event Transient, 
                         Soft-Error Rate, Soft-Error Vulnerability.",
             abstract = "Soft-Error Vulnerability (SEV) is a parameter used to evaluate the 
                         robustness of a circuit to the induced Soft Errors (SEs). There 
                         are many techniques for SEV estimation, including analytical, 
                         electrical and logic simulations, and emulation-based approaches. 
                         Each of them has advantages and disadvantages regarding estimation 
                         time, resources consumption, accuracy, and restrictions over the 
                         analysed circuit. Concerning the ionising radiation effects, some 
                         analytical and electrical simulation approaches take into account 
                         how the circuit topology and the applied input patterns affect 
                         their susceptibilities to Single Event Transient (SET) at the gate 
                         level. On the other hand, logic simulation and emulation 
                         techniques usually ignore these SET susceptibilities. In this 
                         context, we propose a logic simulation-based probability-aware 
                         approach for SEV estimation that takes into account the specific 
                         SET susceptibility of each circuit gate. For a given operational 
                         scenario, we extract the input patterns applied to each gate and 
                         calculate its specific SET susceptibility. For the 38 analysed 
                         benchmark circuits, we obtained a reduction from 15.27% to 0.68% 
                         in the average SEV estimation error, when comparing the estimated 
                         value to a reference obtained at the transistor level. The results 
                         point out an improvement of the SEV estimation process by 
                         considering the specific SET susceptibilities.",
                  doi = "10.3390/electronics8070749",
                  url = "http://dx.doi.org/10.3390/electronics8070749",
                 issn = "1450-5843",
             language = "en",
           targetfile = "armelin_soft.pdf",
        urlaccessdate = "19 abr. 2021"