author = "Benevenuti, F{\'a}bio and Chielle, Eduardo and Tonfat, Jorge and 
                         Tambara, Lucas and Kastensmidt, Fernanda Lima and Zaffari, Carlos 
                         Alberto and Martins, Jo{\~a}o Baptista dos Santos and Dur{\~a}o, 
                         Ot{\'a}vio Santos Cupertino",
          affiliation = "{Universidade Federal do Rio Grande do Sul (UFRGS)} and {New York 
                         University} and {Austrian Academy of ScienceS} and {Cobham Gaisler 
                         AB} and {Universidade Federal do Rio Grande do Sul (UFRGS)} and 
                         {Santa Maria Design House (SMDH)} and {Santa Maria Design House 
                         (SMDH)} and {Instituto Nacional de Pesquisas Espaciais (INPE)}",
                title = "Experimental applications on SRAM-Based FPGA for the NanosatC-BR2 
                         scientific mission",
                 year = "2019",
                pages = "140--146",
         organization = "IEEE International Parallel and Distributed Processing Symposium 
                         Workshops, 33.",
            publisher = "IEEE",
             keywords = "—SRAM-based FPGA, nanosatellite, single-event upsets, fault 
             abstract = "The use of reconfigurable devices, such as FPGAs, in 
                         nanosatellites allows the prototyping and evaluation in flight of 
                         different categories of designs of interest to the aerospace 
                         technology. It includes blending of experimental or well-proven 
                         legacy software executing on microprocessors with out-of-core 
                         accelerators and dedicated logic circuits, or even the conversion 
                         of such software to logic circuits using high-level synthesis 
                         (HLS). An additional feature discussed in this work, which is 
                         relevant to the scientific mission of the NanosatC-BR2 
                         nanosatellite, is the use of SRAM-based FPGA as radiation particle 
                         sensor exploiting the susceptibility of SRAM memory to bit-flips 
                         caused by radiation. The process for bit-flip recording by 
                         bitstream readback is presented as well as a set of experimental 
                         designs implemented on the FPGA for data processing. As the status 
                         of these experimental designs must be reliably tracked by a 
                         supervisory circuit implemented on the same SRAM-based FPGA, 
                         errors caused by the bit-flips must be considered. Mitigation 
                         using triple modular redundancy (TMR) is analyzed using fault 
                         injection, suggesting that a fine grain distributed TMR approach 
                         can increase mission time of the supervisory module by 8x at a 
                         target reliability of 95%, but with a penalty of 40% in the 
                         estimated total power consumption of the FPGA. Conversely, a 
                         blockwise TMR approach can increase mission time of the 
                         supervisory module by 6x at the same target reliability with no 
                         increase in the estimated total power consumption.",
  conference-location = "Rio de Janeiro, Brazil",
      conference-year = "20-24 May",
                  doi = "10.1109/IPDPSW.2019.00032",
                  url = "http://dx.doi.org/10.1109/IPDPSW.2019.00032",
                 isbn = "978-172813510-6",
             language = "en",
           targetfile = "benevenuti_experimental.pdf",
        urlaccessdate = "13 abr. 2021"