author = "Armelin, F{\'a}bio Batagin and Naviner, Lirida A. B. and D'Amore, 
          affiliation = "{Instituto Nacional de Pesquisas Espaciais (INPE)} and Telī ecom 
                         ParisTech, COMELEC and {Instituto Tecnologico de Aeron{\'a}utica 
                title = "Using FPGA self-produced transients to emulate SETs for SER 
            booktitle = "Proceedings...",
                 year = "2018",
                pages = "1",
         organization = "IEEE LatinAmerican Test Symposium, 19. (LATS)",
            publisher = "IEEE",
             abstract = "The application of an electrical pulse to emulate a Single Event 
                         Transient (SET) is a strategy adopted in the study of pulse 
                         broadening and quenching effects. This strategy is usually 
                         restricted to the combinational circuits due to the temporal 
                         masking effect of the clock used in sequential circuits. 
                         Emulation-based fault-injection approaches, which consider the SET 
                         in addition to the SEU (Single Event Upset), do not use electrical 
                         pulses to emulate the SETs. Despite all these restrictions, an 
                         emulation-based fault-injection approach for Soft-Error Rate (SER) 
                         estimation, running on the same device chosen as the final target, 
                         is suitable for real electrical pulses for SET emulation. As the 
                         SER has a statistical nature, the fault-injection method does not 
                         need to control when the SET occurs inside the clock cycle. 
                         Instead, it needs to guarantee that the SET may occur at any 
                         moment, without bias. On the other hand, once using the same 
                         device, the concern about electrical distortion is restricted to 
                         the fault-injection process itself. In this context, this work 
                         presents an analysis of the use of an FPGA self-produced transient 
                         pulse as an emulated SET for SER estimation. The results show that 
                         is feasible to adopt this approach in some particular cases, with 
                         advantages related to the estimation process speed.",
  conference-location = "Sao Paulo, SP",
      conference-year = "12-14 mar.",
                  doi = "10.1109/LATW.2018.8349663",
                  url = "http://dx.doi.org/10.1109/LATW.2018.8349663",
                 isbn = "9781538614723",
                label = "lattes: 9537412416816656 1 ArmelinNaviDAmo:2018:UsFPSe",
             language = "en",
           targetfile = "armelin_using.pdf",
        urlaccessdate = "01 dez. 2020"