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Tipo de ReferênciaArtigo em Evento (Conference Proceedings)
Sitemtc-m16d.sid.inpe.br
Código do Detentorisadg {BR SPINPE} ibi 8JMKD3MGPCW/3DT298S
Identificador8JMKD3MGP7W/3EEK9BL
Repositóriosid.inpe.br/mtc-m19/2013/07.11.16.24   (acesso restrito)
Última Atualização2013:07.12.11.37.22 administrator
Metadadossid.inpe.br/mtc-m19/2013/07.11.16.24.38
Última Atualização dos Metadados2018:06.05.04.14.35 administrator
DOI10.1109/AERO.2013.6497170
ISBN978-1-4673-1811-2
Chave de CitaçãoGuareschiAzKaReDuScDe:2013:CoTeBe
TítuloConfigurable test bed design for nanosats to qualify commercial and customized integrated circuits
Ano2013
Data de Acesso24 fev. 2021
Número de Arquivos1
Tamanho455 KiB
Área de contextualização
Autor1 Guareschi, William
2 Azambuja, Jose
3 Kastensmidt, Fernanda
4 Reis, Ricardo
5 Durão, Otávio Santos Cupertino
6 Schuch, Nelson
7 Dessbesel, Gustavo
Identificador de Curriculo1
2
3
4
5 8JMKD3MGP5W/3C9JJ2L
Grupo1
2
3
4
5 CPA-CPA-INPE-MCTI-GOV-BR
6 CRS-CCR-INPE-MCTI-GOV-BR
Afiliação1 UFRGS, PGMICRO, PPGC, Porto Alegre, RS, Brazil
2 UFRGS, PGMICRO, PPGC, Porto Alegre, RS, Brazil
3 UFRGS, PGMICRO, PPGC, Porto Alegre, RS, Brazil
4 UFRGS, PGMICRO, PPGC, Porto Alegre, RS, Brazil
5 Instituto Nacional de Pesquisas Espaciais (INPE)
6 Instituto Nacional de Pesquisas Espaciais (INPE)
Endereço de e-Mail do Autor1 wnguareschi@inf.ufrgs.br
2 jrfazambuja@inf.ufrgs.br
3 fglima@inf.ufrgs.br
4 reis@inf.ufrgs.br
5 durao@dir.inpe.br
6 njschuch@lacesm.ufsm.br
7 gustavo.dessbesel@smdh.org
Endereço de e-Mailmarcelo.pazos@inpe.br
Nome do EventoIEEE Aerospace Conference.
Localização do EventoBig Sky, Montana, USA
DataMar. 2 - 9, 2013
Título do LivroProceedings
Tipo SecundárioPRE CI
Histórico2013-07-11 16:24:38 :: marcelo.pazos@sid.inpe.br -> administrator ::
2018-06-05 04:14:35 :: administrator -> marcelo.pazos@inpe.br :: 2013
Área de conteúdo e estrutura
É a matriz ou uma cópia?é a matriz
Estágio do Conteúdoconcluido
Transferível1
Tipo do ConteudoExternal Contribution
Tipo de Versãopublisher
Palavras-Chaveadaptive systems, computer hardware description languages, control systems, data transfer, equipment testing, flash memory, flight control systems, hardening, integrated circuits, ionizing radiation, nanosatellites, network protocols.
ResumoThe use of small satellites has increased substantially in recent years due to the reduced cost of their development and launch, as well to the flexibility offered by commercial components. The test bed is a platform that allows components to be evaluated and tested in space. It is a flexible platform, which can be adjusted to a wide quantity of components and interfaces. This work proposes the design and implementation of a test bed suitable for test and evaluation of commercial circuits used in nanosatellites. The development of such a platform allows developers to reduce the efforts in the integration of components and therefore speed up the overall system development time. The proposed test bed is a configurable platform implemented using a Field Programmable Gate Array (FPGA) that controls the communication protocols and connections to the devices under test. The Flash-based ProASIC3E FPGA from Microsemi is used as a control system. This adaptive system enables the control of new payloads and softcores for test and validation in space. Thus, the integration can be easily performed through configuration parameters. It is intended for modularity. Each component connected to the test bed can have a specific interface programmed using a hardware description language (HDL). The data of each component is stored in embedded memories. Each component has its own memory space. The size of the allocated memory can be also configured. The data transfer priority can be set and packaging can be added to the logic, when needed. Communication with peripheral devices and with the Onboard Computer (OBC) is done through the pre-implemented protocols, such as I2C (Inter-Integrated Circuit), SPI (Serial Peripheral Interface) and external memory control. In loco primary tests demonstrated the control system's functionality. The commercial ProASIC3E FPGA family is not space-flight qualified, but tests have been made under Total Ionizing Dose (TID) showing its robustness up to 25 krads (Si). When considering proton and heavy ions, flash-based FPGAs provide immunity to configuration loss and low bit-flips susceptibility in flash memory. In this first version of the test bed two components are connected to the controller FPGA: a commercial magnetometer and a hardened test chip. The embedded FPGA implements a Single Event Effects (SEE) hardened microprocessor and few other soft-cores to be used in space. This test bed will be used in the NanoSatC-BR1, the first Brazilian Cubesat scheduled to be launched in mid-2013.
AreaETES
Arranjo 1Repositório da BDMCI > Fonds INPE > Produção > CRCRS > Configurable test bed...
Arranjo 2Repositório da BDMCI > Fonds INPE > Produção > COGCT > Configurable test bed...
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Arquivo Alvo06497170.pdf
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Área de fontes relacionadas
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Acervo Hospedeirosid.inpe.br/mtc-m19@80/2009/08.21.17.02
Área de notas
Notas2013 IEEE Aerospace Conference, AERO 2013, March 2, 2013 - March 9, 2013
Campos Vaziosaccessionnumber archivingpolicy archivist callnumber copyholder copyright creatorhistory descriptionlevel dissemination edition editor format issn label lineage mark nextedition numberofvolumes orcid organization pages parameterlist parentrepositories previousedition previouslowerunit progress project publisher publisheraddress rightsholder secondarydate secondarykey secondarymark serieseditor session shorttitle sponsor subject tertiarymark tertiarytype type url volume
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