%0 Journal Article
%4 sid.inpe.br/mtc-m21b/2017/03.03.12.58
%2 sid.inpe.br/mtc-m21b/2017/03.03.12.58.27
%@doi 10.1016/j.micpro.2017.01.008
%@issn 0141-9331
%T A tolerant JPEG-LS image compressor foreseeing COTS FPGA implementation
%D 2017
%8 Mar.
%9 journal article
%A Lopes Filho, Antonio,
%A D'Amore, R.,
%@affiliation Instituto Nacional de Pesquisas Espaciais (INPE)
%@affiliation Instituto Tecnológico de Aeronáutica (ITA)
%@electronicmailaddress antonio.lopes@inpe.br
%B Microprocessors and Microsystems
%V 49
%P 54-63
%K COTS FPGA, Fault injection, Fault-tolerance mechanisms, Image compression, LEO, Susceptibility evaluation, VHDL simulations.
%X A compact solution for onboard tolerant image compression is studied and the effectiveness of the soft-error mitigation strategy is evaluated by using a simulation-based susceptibility analysis method. The low complexity JPEG-LS compression algorithm allows considering medium-size flash or antifuse COTS FPGAs as a target for future use in small satellites. Fault mitigation methods, like Triple Modular Redundancy and Hamming code, with scrubbing to mitigate residual error accumulation, were selected taking into account operation in LEO space missions. The results point out the viability of implementing a tolerant image compression system in a single device with two orders-of-magnitude reduction in the susceptibility estimate based on a non-tolerant reference VHDL code. The effectiveness of the mitigation strategy, the injection model accuracy and possible improvements are discussed herein.
%@language en
%3 lopes filho_tolerant.pdf